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<a href="README_8md.html">Go to the documentation of this file.</a><div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;/*! \mainpage AXI Muckbucket</div><div class="line"><a name="l00002"></a><span class="lineno">    2</span>&#160; * \section intro_sec Introduction</div><div class="line"><a name="l00003"></a><span class="lineno">    3</span>&#160; * This is an AXI testbench. It uses UVM so unfortunately iverilog isn&#39;t sufficient. (I hope this changes soon.)</div><div class="line"><a name="l00004"></a><span class="lineno">    4</span>&#160; * - Dual-top testbench</div><div class="line"><a name="l00005"></a><span class="lineno">    5</span>&#160; * - Slave responder, no BFM (currently)</div><div class="line"><a name="l00006"></a><span class="lineno">    6</span>&#160; * - Supports AXI3 and AXI4</div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160; * - Supports all AXI data widths (8,16,32,64,128,256,512 and 1024)</div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160; * - Supports 32-bit and 64-bit address widths</div><div class="line"><a name="l00009"></a><span class="lineno">    9</span>&#160; * - Supports full and partial transfers.</div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160; * - Supports aligned and unaligned transfers.</div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160; * - Supports Fixed, Incrementing and Wrapped transfers.</div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160; * - Supports toggling *ready and *valid. Including AXI-incompatibly mode which randomly asserts and deasserts valid before ready asserts.</div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160; * - Fixed burst_type must be aligned. Unaligned Fixed transfers are not supported.</div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160; * - Testbench side is event driven.  No #&#39;delays, no @clock, etc</div><div class="line"><a name="l00015"></a><span class="lineno">   15</span>&#160; * - Emulator friendly (TB side is event driven. no @clock or # delays)</div><div class="line"><a name="l00016"></a><span class="lineno">   16</span>&#160; * - Pipelined AXI driver</div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160; * - back to back transfers with 0 in-between wait clocks.</div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160; * - Polymorphic interface</div><div class="line"><a name="l00019"></a><span class="lineno">   19</span>&#160; * - params_pkg.sv contains all dut parameters</div><div class="line"><a name="l00020"></a><span class="lineno">   20</span>&#160; * - A master driver - acts as an AXI master</div><div class="line"><a name="l00021"></a><span class="lineno">   21</span>&#160; * - A slave driver  - acts as an AXI slave</div><div class="line"><a name="l00022"></a><span class="lineno">   22</span>&#160; * - Coverage collector</div><div class="line"><a name="l00023"></a><span class="lineno">   23</span>&#160; * - Scoreboard (counts address packets and response packets)</div><div class="line"><a name="l00024"></a><span class="lineno">   24</span>&#160; *</div><div class="line"><a name="l00025"></a><span class="lineno">   25</span>&#160; * Good whitepaper on slave sequences:</div><div class="line"><a name="l00026"></a><span class="lineno">   26</span>&#160; * http://www.verilab.com/files/reactive_slaves_presentation.pdf</div><div class="line"><a name="l00027"></a><span class="lineno">   27</span>&#160; * http://www.verilab.com/files/litterick_uvm_slaves2_paper.pdf</div><div class="line"><a name="l00028"></a><span class="lineno">   28</span>&#160; *</div><div class="line"><a name="l00029"></a><span class="lineno">   29</span>&#160; * Parallel/pipelined driver:</div><div class="line"><a name="l00030"></a><span class="lineno">   30</span>&#160; * https://www.quora.com/What-is-the-best-way-to-model-an-out-of-order-transaction-driver-in-UVM</div><div class="line"><a name="l00031"></a><span class="lineno">   31</span>&#160; *</div><div class="line"><a name="l00032"></a><span class="lineno">   32</span>&#160; * Monitors</div><div class="line"><a name="l00033"></a><span class="lineno">   33</span>&#160; * https://verificationacademy.com/verification-horizons/june-2013-volume-9-issue-2/Monitors-Monitors-Everywhere-Who-Is-Monitoring-the-Monitors</div><div class="line"><a name="l00034"></a><span class="lineno">   34</span>&#160; *</div><div class="line"><a name="l00035"></a><span class="lineno">   35</span>&#160; * verification plan (put in seperate doc):</div><div class="line"><a name="l00036"></a><span class="lineno">   36</span>&#160; * - For each supported data width:</div><div class="line"><a name="l00037"></a><span class="lineno">   37</span>&#160; * -    check all 3 burst_types(e_FIXED, e_INCR, e_WRAP)</div><div class="line"><a name="l00038"></a><span class="lineno">   38</span>&#160; * -    all possible burst_sizes (including invalid, make sure they fail)</div><div class="line"><a name="l00039"></a><span class="lineno">   39</span>&#160; * -    all possible lens (only have a couple coverbins though,or any cross will be too large.)</div><div class="line"><a name="l00040"></a><span class="lineno">   40</span>&#160; * -       min (1),  max, everything in-between ?</div><div class="line"><a name="l00041"></a><span class="lineno">   41</span>&#160; * -    stable *ready</div><div class="line"><a name="l00042"></a><span class="lineno">   42</span>&#160; * -    toggling *ready</div><div class="line"><a name="l00043"></a><span class="lineno">   43</span>&#160; * -    stable *valid</div><div class="line"><a name="l00044"></a><span class="lineno">   44</span>&#160; * -    toggling *valid</div><div class="line"><a name="l00045"></a><span class="lineno">   45</span>&#160; * -    AXI-incompabible *valid toggling (valid deasserts before ready asserts)</div><div class="line"><a name="l00046"></a><span class="lineno">   46</span>&#160; * - back-to-back bursts (aw,w,b,ar,r)</div><div class="line"><a name="l00047"></a><span class="lineno">   47</span>&#160; * - one clock delay between bursts (aw,w,b,ar,r)</div><div class="line"><a name="l00048"></a><span class="lineno">   48</span>&#160; * - serial mode (aw, then w, then b, repeat)   (ar, then r, repeat)</div><div class="line"><a name="l00049"></a><span class="lineno">   49</span>&#160; * - pipelined (multiple aw, then multiple w, then multiple b, repeat)   (multiple ar,then multiple r,repeat)</div><div class="line"><a name="l00050"></a><span class="lineno">   50</span>&#160; *</div><div class="line"><a name="l00051"></a><span class="lineno">   51</span>&#160;*/</div></div><!-- fragment --></div><!-- contents -->
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